Andes Technology

Andes RISC-V CON Silicon Valley

DoubleTree by Hilton Hotel San Jose

Event Date/Time:

Explore Two Dynamic Tracks:

  • Main Conference & Exhibits – Open to all attendees!
  • Developer Track – Hands-on technical training for engineers ( limited seating)

Developer Track – Hands-on Technical Training (Limited Seats!)

Four in-depth, 1-hour sessions designed for engineers who want to dive deep into RISC-V technology. Bring your laptop fully charged!


  • Optimization with RISC-V Vector ISA – Curious about RISC-V Vectors (RVV) but unsure how it works? This session covers the basics and how it boosts vector performance. You will get hands-on experience writing and running vector software using AndeSight tools on RVV-capable processors.
  • IAR Professional Tools for RISC-V – Learn how professional tools can help you debug your application more quickly and efficiently, accelerating your time to market. Also, discover how prequalified Functional Safety tools can enhance your products.
  • Create Your Own RISC-V Custom Instructions – Want to create your own RISC-V Instructions to accelerate your application? This session explores Andes’ Automated Custom Extensions (ACE) for enhancing the RISC-V ISA, with a hands-on demo using Andes Copilot, which automates much of the process.
  • Unleashing the Power of Heterogeneous Computing: Building a complex SoC with high compute and memory demands? Avoid performance surprises by understanding how CPU and GPU subsystems interact under real workloads and memory hierarchies. This session demonstrates how trace-based simulation can uncover bottlenecks, validate compute and cache architecture decisions, and improve heterogeneous system performance.



 

Main Conference & Exhibits –


Spotlight on Main Conference

  • Frans Sijstermans, Vice President MultiMedia Architecture/ ASIC, Nvidia – Use of RISC-V in NVIDIA’s Deep-Learning Accelerator
  • Frankwell Lin, Chairman and CEO, Andes Technology – Celebrating 20 Years of Andes: Driving RISC-V Innovation.
  • Charlie Su, President and CTO, Andes Technology – Provides insights on advancing modern computing with Andes RISC-V processor solutions.
  • Paul Master, Co-founder and CTO, Cornami – Presenting Fully Homomorphic Encryption, the Holy Grail.


Connect, Learn, and Network

  • Hear from top industry leaders about the latest advancements in RISC-V.
  • Explore cutting-edge exhibits from companies including Andes, Baya, BrainChip, Cornami, Cycuity, EdgeQ, IAR, QuickLogic, Siemens, and more.
  • Gain insights into real-world applications in AI, Automotive, Application Processing, Communications, and Security.
  • Enjoy extended networking breaks, lunch, and an evening reception.




Fireside Chat: Edge-AI of Tomorrow

Unlocking Commercial Success for Advanced AI


“Edge AI: How We Achieve Scale”

– Jeff Bier, Founder, Edge AI and Vision Alliance


“Edge AI: What’s Working for Commercial Deployments? “ 

– Pete Warden, CEO, Useful Sensors


Join the dialogues with Charlie Cheng, Jeff Bier, and Pete Warden to explore edge-AI breakthroughs, adoption hurdles, and winning strategies for real-world commercial success.


Look forward to seeing you at Andes RISC-V CON Silicon Valley!